/**
 * COPYRIGHT
 * ---------------------------------------------------------------------------------------------------------------------
 * Copyright (c) iSOFT INFRASTRUCTURE SOFTWARE CO., LTD. This software is proprietary to
 * iSOFT INFRASTRUCTURE SOFTWARE CO., LTD., and all rights are reserved by iSOFT INFRASTRUCTURE SOFTWARE CO., LTD.
 * Without the express written permission of the company, no organization or individual may copy, install, trial,
 * distribute, or reverse engineer this software. For terms of use and further details, please refer to the End User
 * License Agreement (EULA) or contact us business@i-soft.com.cn for more assistance.
 *
 * This file contains code from iSoft, which is licensed under the LGPL-2.1. However, due to a special exception,
 * you are not required to comply with the provisions of section 6a of LGPL-2.1. Specifically, you may distribute
 * your software, including this file, under terms of your choice, including proprietary licenses, without needing to
 * provide the source code or object code as specified in section 6a. For more details, please refer to the project's
 * LICENSE and EXCEPTION files and the specific exception statement.
 * ---------------------------------------------------------------------------------------------------------------------
 * FILE DESCRIPTION
 * ---------------------------------------------------------------------------------------------------------------------
 * @MCU               : S32K148
 * @file              : Os_CoreCfg.c
 * @license           : Evaliation
 * @licenseExpiryDate : 
 * @date              : 2025-06-19 10:52:15
 * @customer          : iSoft
 * @description       : Configuration parameter of OS
 * @toolVersion       : 2.2.0.1
 **********************************************************************************************************************/

#include "Os_CoreCfg.h"
#include "Arch_Processor.h"
#include "Os_Cfg.h"
#include "Os_Internal.h"

/*========================[M A C R O S]=======================================*/
#define     OS_ARCH_INT_CORE0              OS_ARCH_INT_CPU0

/* =======================Interrupt install================================== */
/* PRQA S 1532,2016,0303,3432++ */ /* MISRA Rule 8.7,16.4,11.4,20.7 */
#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE) Os_IntHandler(void)
{
    /* Just ignore this interrupt.  */
    while(1) /*PRQA S 2740*/ /* MISRA CWE-569,CWE-571 */
    {
    }
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"

#define OS_START_SEC_CODE_FAST
#include "Os_MemMap.h"
FUNC(void, OS_CODE) Os_ArchInitIntPrio(void)
{
    Os_CoreIdType coreID = Os_SCB.sysCore;
    /*PRQA S 3120++ *//* MISRA DCL06,CWE-398 */
    switch(coreID)
    {
        case OS_CORE_ID_0:
                Os_InterruptInstall(OS_ISR_SysTick_ADDR, 10U, OS_ARCH_INT_CORE0, Os_ISR_OsTimerSourceCore_0_Handler0);
                Os_InterruptInstall(OS_ISR_CAN0_ORed_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed_ADDR_Handler);
                Os_InterruptInstall(OS_ISR_CAN0_ORed_0_15_MB_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed_0_15_MB_ADDR_Handler);
                Os_InterruptInstall(OS_ISR_CAN0_ORed_16_31_MB_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_CAN0_ORed_16_31_MB_ADDR_Handler);
                Os_InterruptInstall(OS_ISR_FTM0_Ch0_Ch1_ADDR, 1U, OS_ARCH_INT_CORE0, Os_ISR_FTM0_Ch0_Ch1_ADDR_Handler);
        break;

        default:
		while(1) /*PRQA S 2740*/ /* MISRA CWE-569,CWE-571 */
		{
		    /*nothing to do*/
		}
        break;
    }
    /*PRQA S 3120-- *//* MISRA DCL06,CWE-398 */
    return;
}
#define OS_STOP_SEC_CODE_FAST
#include "Os_MemMap.h"
